Methods of electrically clocking integrated circuit chips are well known in the art. Typically, an integrated circuit chip mounted on a substrate has one or more chip pads dedicated to receiving electrical clock signals. A typical electrical clock signal path is: From an edge connector pin on a printed circuit board; over printed circuit wiring; through a pin on a module substrate; over substrate wiring; to a pad in a chip mounting location where solder or a wire bond provides an electrical connection between the substrate and the chip. This electrical clock signal is connected to a receiver on the chip that drives and redistributes the clock on the chip.
Electrical clock distribution methods have several problems. First, while a clock signal may come to a single pin on the substrate from the printed circuit card, when the clock is distributed to different chips on the substrate, it does not reach all chips simultaneously because there is a different delay for each clock path. Since each clock path has a different delay, the clock edges reach different chips at slightly different times, therefore, the clock edges are skewed. Ideally, the clock edges should be unskewed for all chips, i.e., the edges reach every module chip simultaneously. Because the clock edges reach different chips at different times, skew causes timing variations for different chips on the same substrate. To compensate for skew in these prior art multi-chip modules, a settling time was added to offset the clock skew. The settling time, which sets the lower limit for a clock period, limits maximum clock frequency, thereby limiting circuit performance.
Skew problems aside, distributing the clock around the substrate to different chips is complicated. Usually the clock wiring must be distributed on several different wiring layers. Consequently, this complicated multi-layer clock wiring has: A high capacitive load resulting from the capacitance between wiring on the different layers; A high inductance loading; and suffers from transmission line effects, all of which exacerbate skew.
Electrically distributed clocks are also sensitive to electromagnetic noise. Electromagnetic noise coupled from adjacent substrate signal lines to the clock lines could cause noise spikes large enough to produce false clock pulses or ghosts. These false clock pulses may cause inadvertent changes in the chip's state. Since these pulses are inadvertent, they are hard to detect, nearly impossible to correct, and very often lead to intermittent timing errors. Intermittent timing errors have caused whole projects to be scrapped.
A second prior art approach to clock distribution is to route the clock optically through optical fibers on the substrate. An optical clock signal is directed through the optical fiber to an optical receiver on the chip. The receiver converts the optical clock signal to an electrical clock signal that is distributed on the chip. Although this approach solved the skew, distribution, and electromagnetic noise problems encountered with the electrical clock distribution, attaching optical fibers to the substrate also had drawbacks.
First, optical fibers use valuable wiring real estate. Typically, electrical wiring lands are 2 mils wide. An optical fiber is 6-12 mils. Thus, each optical fiber uses three or four wiring channels creating blockages in the wiring layer and reducing the number of available wiring channels. Consequently, the number of layers required to wire the other signals between chips is increased. Furthermore, optical fibers do not bend easily. Thus, routing optical clocks to multiple locations quickly becomes unfeasible. Attaching optical fibers to the substrate is difficult, expensive, and the substrates are not reworkable.